`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Arizona State University
// Engineers: Brentton Garber, Georgii Tkachuk
// 
// Create Date: 17:28:56 04/01/2013 
// Design Name: clock_divider
// Module Name: clock_divider
// Project Name: Lab 3
// Target Devices: Xilinx Spartan6 XC6LX16-CS324 
// Tool versions: Xilinx ISE 14.2 
// Description: Divides the clock in half
//
// Revision: 1
// Revision 0.01 - File Created
//
//////////////////////////////////////////////////////////////////////////////////

module clock_divider(
	 input reset,	
    input wire full_clk,
    output wire  half_clk
    );
assign half_clk = d1;

reg d1;

// on positive edge of clock, delay the clock cycle by half
always @(posedge full_clk or negedge reset)
begin
	if (~reset)
	begin
		d1 <= 0;
	end
	else 
		d1 <= ~d1;
end
endmodule